The field-effect transistor is another type of solid-state device that is becoming increasingly popular in electronic circuits. These transistors derive their name from the fact that current flow in them is controlled by variation of an electric field established by application of a voltage to a control electrode, referred to as the gate. In contrast, current flow in bipolar transistors is controlled by variation of the current injected into the base terminal. Moreover, the performance of bipolar transistors depends on the interaction of two types of charge carriers (holes and electrons). Field-effect transistors, however, are unipolar devices; as a result, their operation is basically a function of only one type of charge carrier, holes in p-channel devices and electrons in n-channel devices.

A charge-control concept can be used to explain the basic operation of field-effect transistors. A charge on the gate (control electrode) induces an equal, but opposite, charge in a semiconductor layer, referred to as the channel, located directly beneath the gate. The charge induced in the channel controls the conduction of current through the channel and, therefore, between the source and drain terminals which are connected to opposite ends of the channel.

Discrete-device field-effect transistors are classified, on the basis of their control-gate construction, as either junction-gate types or metal-oxide-semiconductor types. Although both types operate on the basic principle that current conduction is controlled by variation of an electric field, the significant difference in their gate construction results in unique characteristics and advantages for each type.

Junction-Gate Types
Junction-gate field-effect transistors, which are commonly referred to as JFET's, may be either n-channel or p-channel devices. Fig. 21 shows the structure of an p-channel junction-gate field-effect transistor, together with the schematic symbols for both n-channel and p-channel versions of these devices. The structure for a p-channel device is identical to that of an n-channel device with the exception that n- and p-type semiconductor materials are replaced by p- and n-type materials, respectively. In both types of junction-gate devices, a thin channel under the gate provides a conductive path between the source and drain terminals with zero gate-bias voltage. A p-n junction is formed at the interface of the gate and the source-to-drain layer. When this junction is reverse-biased, current conduction in the channel between the source and drain terminals is controlled by the magnitude of reverse-bias voltage, which if sufficientcan virtually cut off the flow of current through the channel.

 If the junction becomes forward-biased, the input resistance (i.e., resistance between the gate and the source-to-drain layer) decreases sharply, and an appreciable amount of gate current flows. Under such conditions, the gate loading reduces the amplitude of the input signal, and a significant reduction in power gain results. This characteristic is a major disadvantage of junction-gate field-effect transistors. Another undesirable feature of these devices is that the leakage currents across the reverse-biased p-n junction can vary markedly with changes in ambient temperature. This latter factor tends to complicate circuit design considerations. Nonetheless, the junction-gate field-effect transistor is a very useful device in many small-signal-amplifier and chopper applications.

Metal-Oxide-Semiconductor Types
Figs. 22 and 23 shows the structures and schematic symbols for both enhancement and depletion types of metal-oxide-semiconductor field-effect transistors (MOS/FET's). In these devices, the metallic gate is electrically insulated from the semiconductor surface by a thin layer of silicon dioxide. These devices, which are commonly referred to as MOS field-effect transistors or, more simply, as MOS transistors, derive their name from the tri-layer construction of metal, oxide, and semiconductor material. Insulation of the gate from the remainder of the transistor structure results in an exceedingly high input resistance (i.e., in the order of 10¹⁴ ohms). It should be realized that the metal gate and the semiconductor channel form a capacitor in which the oxide layer serves as the dielectric insulator.

The marked differences in the construction of enhancement and depletion types of MOS field-effect transistors, as is apparent from a comparison of Figs. 22(a) and 23(a), results in significant differences in the characteristics of these devices and, therefore, in the applications in which they are normally employed.

As indicated by the interruptions in the channel line of the schematic symbols shown in Fig. 22(b), enhancement-type MOS field-effect transistors are characterized by the fact that they have a "normally open" channel so that no useful channel conductivity exists for either zero or reverse gate bias.

Consequently, this type of device is ideal for use in digital and switching applications. The gate of the enhancement type of MOS field-effect transistor must be forward-biased with respect to the source to produce the active charge carriers in the channel required for conduction. When sufficient forward-bias (positive) voltage is applied to the gate of an n-channel device, the region under the gate changes from p-type to n-type and provides a conduction path between the n-type source and drain regions. Similarly, in p-channel devices, application of sufficient negative gate voltage draws holes into the region below the gate so that this channel region changes from n-type to p-type to provide a source-to-drain conduction path.

Depletion-type MOS field-effect transistors are characterized by the fact that, with zero gate bias, the thin channel under the gate region provides a conductive path between the source and drain terminals. In the schematic symbols for these devices, shown in Fig. 23 (b), the channel line is drawn continuous to indicate this "normally on" condition. When the gate is reverse-biased (negative with respect to the source for n-channel devices, or positive with respect to the source for p-channel devices), the channel can be depleted of charge carriers; conduction in the channel, therefore, can be cut off if the gate potential is sufficiently high.

A unique characteristic of depletion-type MOS transistors is that additional charge carriers can be produced in the channel and, therefore, conduction in the channel can be increased by application of forward bias to the gate. No reduction in power gain occurs under these conditions, as is the case in junction-gate field-effect transistors, because the oxide insulation between the gate and the source-to-drain layer blocks the flow of gate current even when the gate is forward-biased.

The diagram shown in Fig. 23(a) illustrates the structure of a single-gate depletion-type MOS field-effect transistor. Depletion-type MOS field-effect transistors that have two independent insulated gate electrodes are also available. These devices offer unique advantages and represent the most important category of MOS field-effect transistors.

Fig. 24(a) shows a cross-sectional diagram of an n-channel depletion-type dual-gate MOS field-effect transistor. The transistor includes three terminating (n-diffused) regions connected by two conductive channels, each of which is controlled by its own independent gate terminal. For convenience of explanation, the transistor is shown divided into two units. Unit No. 1 consists of the source, gate No. 1, channel No. 1, and the central n-region which function as drain No.1. These elements act as a conventional single-gate depletion-type MOS field-effect transistor for which unit No.2 functions as a load resistor. Unit No. 2 consists of the central n-region, which functions as source No.2, gate No. 2, channel No.2, and the drain. This unit may also be used as an independent single-gate transistor for which unit No. 1 acts as a source resistor. Fig. 24(b) shows the schematic symbol for an n-channel dual-gate MOS field-effect transistor.

Equivalent-circuit representations of the two units in a dual-gate MOS transistor are shown in Fig. 25. Current can be cut off if either gate is sufficiently reverse-biased with respect to the source. When one gateis biased to cutoff, a change in the voltage on the other gate is equivalentto a change in the value of a resistor in series with a cut-off transistor. The dual-gate MOS field-effect transistor provides exceptional versatility for circuit applications. The independent pair of gates makes this device attractive for use in rf amplifiers, gain-controlled amplifiers, mixers, and demodulators. In a gain-controlled amplifier, the signal is applied to gate No.1, and the gain-control voltage is applied to gate No. 2. This arrangement is recommended because the forward transconductance obtained with gate No. 1 is higher than that obtained with gate No.2. Moreover, unit No.2 is very effective for isolation of the drain and gate No. 1. This unit provides sufficient isolation so that the dual-gate devices can be operated at frequencies into the uhf range without the need for neutralization.

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